发明授权
US08722511B2 Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric
有权
通过在形成层间电介质之前施加沉积/蚀刻顺序来减少半导体器件的隔离区域的形貌
- 专利标题： Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric
- 专利标题（中）： 通过在形成层间电介质之前施加沉积/蚀刻顺序来减少半导体器件的隔离区域的形貌
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申请号： US13154754申请日： 2011-06-07
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公开(公告)号： US08722511B2公开(公告)日： 2014-05-13
- 发明人: Ralf Richter , Peter Javorka , Kai Frohberg
- 申请人： Ralf Richter , Peter Javorka , Kai Frohberg
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Amerson Law Firm, PLLC
- 优先权： DE102010038746 20100730
- 主分类号： H01L21/76
- IPC分类号： H01L21/76
摘要：
Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.
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