公开(公告)号：US08722511B2

公开(公告)日：2014-05-13

申请号：US13154754

申请日：2011-06-07

申请人： Ralf Richter ,  Peter Javorka ,  Kai Frohberg

发明人： Ralf Richter ,  Peter Javorka ,  Kai Frohberg

IPC分类号： H01L21/76

CPC分类号： H01L23/485 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

摘要： Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.

摘要翻译： 复杂的半导体器件中的接触故障可以通过在沉积层间绝缘材料系统之前放宽隔离区域中显着的表面形貌来降低。 为此，可以施加沉积/蚀刻顺序，其中填充材料可以从有源区域移除，而隔离区域中的凹部可以至少部分地被填充。

公开(公告)号：US20120025318A1

公开(公告)日：2012-02-02

申请号：US13154754

申请日：2011-06-07

申请人： Ralf Richter ,  Peter Javorka ,  Kai Frohberg

发明人： Ralf Richter ,  Peter Javorka ,  Kai Frohberg

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L23/485 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

摘要： Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.

摘要翻译： 复杂的半导体器件中的接触故障可以通过在沉积层间绝缘材料系统之前放宽隔离区域中显着的表面形貌来降低。 为此，可以施加沉积/蚀刻顺序，其中填充材料可以从有源区域移除，而隔离区域中的凹部可以至少部分地被填充。

公开(公告)号：US09224863B2

公开(公告)日：2015-12-29

申请号：US13483481

申请日：2012-05-30

申请人： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

发明人： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC分类号： H01L27/095 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

摘要： In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.

摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段提供的高k金属栅电极结构的基础上形成晶体管，其中可以通过使用嵌入式应变诱导半导体合金来实现有效的应变诱导机制。 为了减少晶格缺陷的数量并且在临界区域（即，阈值电压调节半导体合金和应变诱导半导体材料位于紧邻的区域）提供增强的蚀刻电阻率，可以使用有效的缓冲材料或 引入种子材料，例如硅材料，其可以在选择性外延生长过程期间完成。

公开(公告)号：US08939765B2

公开(公告)日：2015-01-27

申请号：US12965118

申请日：2010-12-10

申请人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

发明人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。

公开(公告)号：US08836047B2

公开(公告)日：2014-09-16

申请号：US13421394

申请日：2012-03-15

申请人： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

发明人： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC分类号： H01L27/04 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.

摘要翻译： 当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。 为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。

公开(公告)号：US08735303B2

公开(公告)日：2014-05-27

申请号：US13287403

申请日：2011-11-02

申请人： Hans-Juergen Thees ,  Stephan Kronholz ,  Peter Javorka

发明人： Hans-Juergen Thees ,  Stephan Kronholz ,  Peter Javorka

IPC分类号： H01L21/31

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L27/108 ,  H01L27/10894 ,  H01L29/1033

摘要： One illustrative method disclosed herein includes forming a first recess in a first active region of a substrate, forming a first layer of channel semiconductor material for a first PFET transistor in the first recess, performing a first thermal oxidation process to form a first protective layer on the first layer of channel semiconductor material, forming a second recess in the second active region of the semiconducting substrate, forming a second layer of channel semiconductor material for the second PFET transistor in the second recess and performing a second thermal oxidation process to form a second protective layer on the second layer of channel semiconductor material.

摘要翻译： 本文公开的一种说明性方法包括在衬底的第一有源区中形成第一凹槽，在第一凹槽中形成用于第一PFET晶体管的沟道半导体材料的第一层，执行第一热氧化工艺以形成第一保护层 所述第一沟道半导体材料层在所述半导体衬底的所述第二有源区中形成第二凹槽，在所述第二凹槽中形成用于所述第二PFET晶体管的沟道半导体材料的第二层，并执行第二热氧化工艺以形成第二层 沟道半导体材料的第二层上的保护层。

公开(公告)号：US08536009B2

公开(公告)日：2013-09-17

申请号：US13197239

申请日：2011-08-03

申请人： Peter Javorka ,  Maciej Wiatr ,  Stephan-Detlef Kronholz

发明人： Peter Javorka ,  Maciej Wiatr ,  Stephan-Detlef Kronholz

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/82385

摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.

摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段提供高k金属栅极电极结构，其中P沟道晶体管的阈值电压调节可以基于阈值电压调节半导体合金（诸如硅/锗） 合金，用于长沟道器件，而在硅/锗合金的选择性外延生长期间可能会掩蔽短沟道器件。 在一些说明性实施例中，阈值电压调整可以在没有用于P沟道晶体管的任何晕圈注入工艺的情况下完成，而阈值电压可以通过N沟道晶体管的晕圈注入来调节。

公开(公告)号：US08497180B2

公开(公告)日：2013-07-30

申请号：US13204271

申请日：2011-08-05

申请人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

发明人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L29/6653 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers.

摘要翻译： 器件形成有通过各向同性蚀刻然后进行各向异性蚀刻形成的引线形状的源极/漏极区域。 实施例包括在衬底上形成栅极，在栅极的每一侧上形成第一间隔物，在栅极的每一侧上在衬底中形成源极/漏极区域，其中每个源极/漏极区域在第一间隔物之下延伸，但是 由基板的一部分与之隔开，并具有基本上水平的底面。 实施例还包括通过将空腔形成为与第一间隔件相邻的第一深度并形成第二腔至第一腔的第二深度并且在第一间隔物下方横向延伸来形成每个源/漏区。

公开(公告)号：US20130032901A1

公开(公告)日：2013-02-07

申请号：US13204283

申请日：2011-08-05

申请人： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L21/336 ,  H01L29/78 ,  B82Y40/00

CPC分类号： H01L29/66507 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7845

摘要： Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

公开(公告)号：US20100155850A1

公开(公告)日：2010-06-24

申请号：US12710744

申请日：2010-02-23

申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

IPC分类号： H01L27/092

CPC分类号： H01L29/66628 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684

摘要： By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

摘要翻译： 通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。 此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。