A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file.