Invention Grant
- Patent Title: Generating optimal instruction sequences for bitwise logical expressions
- Patent Title (中): 为按位逻辑表达式生成最优指令序列
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Application No.: US12308479Application Date: 2006-06-30
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Publication No.: US08732686B2Publication Date: 2014-05-20
- Inventor: Konstantin S. Serebryany
- Applicant: Konstantin S. Serebryany
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakey, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/RU2006/000346 WO 20060630
- International Announcement: WO2008/002177 WO 20080103
- Main IPC: G06F9/45
- IPC: G06F9/45

Abstract:
A sequence generator generates a table of optimal instruction sequences for all bitwise expression having a specific number of variables. An index generator generates a bit-string index that corresponds to a particular bitwise expression. The bit-string is generated from a truth table. A table lookup unit is coupled with the index generator. The table lookup unit finds an optimal instruction sequence for the bitwise expression from within the table of optimal instruction sequences based at least in part on the generated bit-string index.
Public/Granted literature
- US20100275192A1 Generating optimal instruction sequences for bitwise logical expressions Public/Granted day:2010-10-28
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