发明授权
US08735050B2 Integrated circuits and methods for fabricating integrated circuits using double patterning processes
有权
用于使用双重图案化工艺制造集成电路的集成电路和方法
- 专利标题： Integrated circuits and methods for fabricating integrated circuits using double patterning processes
- 专利标题（中）： 用于使用双重图案化工艺制造集成电路的集成电路和方法
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申请号： US13567233申请日： 2012-08-06
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公开(公告)号： US08735050B2公开(公告)日： 2014-05-27
- 发明人: Lei Yuan , Hidekazu Yoshida , Jongwook Kye , Qi Xiang , Mahbub Rashed
- 申请人： Lei Yuan , Hidekazu Yoshida , Jongwook Kye , Qi Xiang , Mahbub Rashed
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES, Inc.
- 当前专利权人： GLOBALFOUNDRIES, Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Ingrassia Fisher & Lorenz, P.C.
- 主分类号： G03F1/00
- IPC分类号： G03F1/00 ; G06F17/50
摘要：
Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.
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