Forming wafer-level chip scale package structures with reduced number of seed layers

发明授权

US08735273B2 Forming wafer-level chip scale package structures with reduced number of seed layers 有权

标题翻译：形成具有减少种子层数的晶片级芯片级封装结构

请登陆查看更多内容

专利标题： Forming wafer-level chip scale package structures with reduced number of seed layers
专利标题（中）： 形成具有减少种子层数的晶片级芯片级封装结构
申请号： US13179299

申请日： 2011-07-08
公开(公告)号： US08735273B2

公开(公告)日： 2014-05-27
发明人: Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
申请人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
申请人地址： TW Hsin-Chu
专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
当前专利权人地址： TW Hsin-Chu
代理机构： Slater and Matsil, L.L.P.
主分类号： H01L21/44
IPC分类号： H01L21/44

Forming wafer-level chip scale package structures with reduced number of seed layers

摘要：

A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

摘要（中）：

一种方法包括在覆盖半导体衬底的金属焊盘上形成钝化层。在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。种子层形成在钝化层之上并且电耦合到金属焊盘。种子层还包括钝化层上的部分。在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。在种子层和第二开口中形成PPI。在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。金属凸块的一部分形成在第三开口中。在形成金属凸块的部分的步骤之后，去除第一和第二掩模。

公开/授权文献

US20130009307A1 Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers 公开/授权日：2013-01-10

信息查询

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/44	....用H01L21/36至H01L21/428各组不包含的方法或设备在半导体材料上制造电极的