公开(公告)号：US10784221B2

公开(公告)日：2020-09-22

申请号：US13312395

申请日：2011-12-06

Applicant: Hsiu-Jen Lin ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Chung-Cheng Lin ,  Yu-Peng Tsai ,  Cheng-Ting Chen

Inventor： Hsiu-Jen Lin ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Chung-Cheng Lin ,  Yu-Peng Tsai ,  Cheng-Ting Chen

IPC: H01L21/58 ,  H01L23/00 ,  H05K3/34 ,  H05K3/28 ,  H01L21/48

Abstract: A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

公开(公告)号：US09991190B2

公开(公告)日：2018-06-05

申请号：US13475674

申请日：2012-05-18

Applicant: Hui-Min Huang ,  Yen-Chang Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

Inventor： Hui-Min Huang ,  Yen-Chang Hu ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/495 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.

公开(公告)号：US09786622B2

公开(公告)日：2017-10-10

申请号：US13277575

申请日：2011-10-20

Applicant: Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/1601 ,  H01L2224/16104 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.

公开(公告)号：US09543185B2

公开(公告)日：2017-01-10

申请号：US13309311

申请日：2011-12-01

Applicant: Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: B23Q3/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75754 ,  H01L2224/7698 ,  H01L2224/81001 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83102 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/013

Abstract: Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Abstract translation: 公开了用于半导体器件的封装加工工具和系统以及封装方法。 在一个实施例中，用于半导体器件的封装处理工具包括用于在集成电路管芯的封装工艺期间支撑封装衬底或集成电路管芯的机械结构。 机械结构包括设置在其上的低热导率材料。

公开(公告)号：US09536818B2

公开(公告)日：2017-01-03

申请号：US13272434

申请日：2011-10-13

Applicant: Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/498 ,  B23K1/20 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49894 ,  H01L21/4864 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.

Abstract translation: 半导体封装的方法包括提供具有涂覆有有机可焊性防腐剂（OSP）层的导电迹线的衬底，从导电迹线去除OSP层，然后将芯片耦合到衬底以形成半导体封装。

公开(公告)号：US09059109B2

公开(公告)日：2015-06-16

申请号：US13427787

申请日：2012-03-22

Applicant: Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure.

Abstract translation: 一种包装组件，其包括通过互连的接合结构电耦合到衬底的半导体管芯。 半导体管芯包括覆盖半导体衬底的凸块和覆盖半导体衬底并与凸点的第一部分物理接触的模塑复合层。 衬底包括导电区域上的无流动底部填充层。 凸块的第二部分与无流动底部填充层物理接触以形成互连的连接结构。

公开(公告)号：US08878352B2

公开(公告)日：2014-11-04

申请号：US13357379

申请日：2012-01-24

Applicant: Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

Inventor： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/02

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

公开(公告)号：US08703546B2

公开(公告)日：2014-04-22

申请号：US12784314

申请日：2010-05-20

Applicant: Chih-Wei Lin ,  Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Chih-Wei Lin ,  Ming-Da Cheng ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L21/82 ,  H01L21/288

CPC classification number: H01L21/288 ,  C25D7/123 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/93 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/1146

Abstract: A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.

Abstract translation: 一种形成装置的方法包括进行第一电镀工艺以形成第一金属特征，并且在活化处理溶液中对第一金属特征的表面进行活化处理，其中活化处理溶液包括处理剂， 电离（DI）水。 在执行激活处理的步骤之后，执行第二电镀处理以形成第二金属特征并接触第一金属特征的表面。

公开(公告)号：US20140061932A1

公开(公告)日：2014-03-06

申请号：US13604333

申请日：2012-09-05

Applicant: Meng-Tse Chen ,  Yi-Da Tsai ,  Xi-Hong Chen ,  Tao-Hua Lee ,  Wei-Yu Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Yi-Da Tsai ,  Xi-Hong Chen ,  Tao-Hua Lee ,  Wei-Yu Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/28 ,  H01L21/78 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Abstract translation: 提供封装封装（“PoP”）结构和形成方法。 PoP结构可以通过在第一基板上形成第一组电连接而形成。 可以将第一材料施加到第一组电连接。 可以提供具有形成在其上的第二组电连接的第二基板。 具有施加的环氧树脂焊剂的第一基板的第一组电连接可以接触第二基板的第二电连接。 可以进行回流工艺以将第一衬底电连接到第二衬底。 施加到第一基板的第一电连接处的环氧树脂通量可能会在回流过程中阻止电桥或短路的形成。

公开(公告)号：US20140048934A1

公开(公告)日：2014-02-20

申请号：US13586564

申请日：2012-08-15

Applicant: Meng-Tse Chen ,  Jung Wei Cheng ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Jung Wei Cheng ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L2224/16225

Abstract: A semiconductor device assembly includes a substrate having an area of the surface treated to form a surface roughness. A die is mounted on the substrate by a plurality of coupling members. An underfill substantially fills a gap disposed between the substrate and the die, wherein a fillet width of the underfill is substantially limited to the area of surface roughness.

Abstract translation: 半导体器件组件包括具有被处理以形成表面粗糙度的表面区域的衬底。 模具通过多个联接构件安装在基板上。 底部填充物基本上填充设置在基底和模具之间的间隙，其中底部填充物的圆角宽度基本上限于表面粗糙度的面积。