A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit.