公开(公告)号：US08296499B2

公开(公告)日：2012-10-23

申请号：US11950303

申请日：2007-12-04

申请人： You-Sung Kim ,  Byung-Ryul Kim

发明人： You-Sung Kim ,  Byung-Ryul Kim

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A flash memory device includes a memory cell array, a peri circuit unit, an I/O controller, and a controller. The memory cell array includes a plurality of memory cells respectively connected to a plurality of bit line pairs and a plurality word lines. The peri circuit unit is configured to program data into the memory cell array or read data stored in the memory cell array in response to a command input through a control bus. The I/O controller is configured to receive data for programming and supply the data to the peri circuit unit in response to a command provided through a data input/output (I/O) bus. The controller is configured to control the I/O controller to perform a voltage setup operation for a program while the data for program is received.

摘要翻译： 闪存器件包括存储单元阵列，周边电路单元，I / O控制器和控制器。 存储单元阵列包括分别连接到多个位线对和多个字线的多个存储单元。 周边电路单元被配置为响应于通过控制总线输入的命令，将数据编程到存储单元阵列中或读取存储在存储单元阵列中的数据。 I / O控制器被配置为接收用于编程的数据，并响应于通过数据输入/输出（I / O）总线提供的命令将数据提供给周边电路单元。 控制器被配置为控制I / O控制器，以便在接收到用于节目的数据时对节目执行电压设置操作。

公开(公告)号：US08107291B2

公开(公告)日：2012-01-31

申请号：US12702205

申请日：2010-02-08

申请人： You Sung Kim ,  Duck Ju Kim

发明人： You Sung Kim ,  Duck Ju Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5642

摘要： A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block is received. The plurality of pages is programmed in a predefined order. An address corresponding to a page that was programmed last amongst the plurality of pages is stored.

摘要翻译： 公开了一种在闪速存储器件中编程数据的方法。 存储器件包括存储单元阵列，该存储单元阵列又包括至少一个块，并且该块又包括多个页。 接收用于对块中的多个页面进行编程的程序命令。 多个页面以预定义的顺序被编程。 存储与多个页面中最后编程的页面相对应的地址。

公开(公告)号：US07986552B2

公开(公告)日：2011-07-26

申请号：US12400847

申请日：2009-03-10

申请人： Tao Ho Shin ,  Joong Seob Yang ,  Jun Seop Chung ,  You Sung Kim

发明人： Tao Ho Shin ,  Joong Seob Yang ,  Jun Seop Chung ,  You Sung Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C16/10

摘要： A nonvolatile memory device includes a data conversion unit including an encoder and a decoder. The encoder sets data for each of word lines and creates second data to be programmed into a plurality of memory cells by performing a logical operation on the set data and first data input for programming. The decoder creates the first data by performing a logical operation on the second data that is read from the memory cells and the set data.

摘要翻译： 一种非易失性存储器件包括一个包括一个编码器和一个解码器的数据转换单元。 编码器为每个字线设置数据，并且通过对设置数据执行逻辑运算并将第一数据输入用于编程来创建要编程到多个存储器单元中的第二数据。 解码器通过对从存储器单元读取的第二数据和设置数据执行逻辑运算来创建第一数据。

公开(公告)号：US07864590B2

公开(公告)日：2011-01-04

申请号：US12117702

申请日：2008-05-08

申请人： You Sung Kim ,  Tae Ho Shin

发明人： You Sung Kim ,  Tae Ho Shin

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10

摘要： A non-volatile memory device includes a memory cell array and a controller. The memory cell array includes memory cells for data storage and a plurality of flag cells. The flag cells indicate program states of the memory cells for each of a plurality of word lines. The controller determines the program states of the memory cells by employing the flag cells and controls a pass voltage provided to a corresponding word line according to the determined program states.

摘要翻译： 非易失性存储器件包括存储单元阵列和控制器。 存储单元阵列包括用于数据存储的存储单元和多个标志单元。 标志单元表示多个字线中的每一个的存储单元的编程状态。 控制器通过采用标志单元来确定存储器单元的编程状态，并且根据所确定的程序状态控制提供给相应字线的通过电压。

公开(公告)号：US20100135076A1

公开(公告)日：2010-06-03

申请号：US12702199

申请日：2010-02-08

申请人： You Sung Kim ,  Duck Ju Kim

发明人： You Sung Kim ,  Duck Ju Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5642

摘要： A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.

摘要翻译： 公开了一种在闪速存储器件中执行读取操作的方法。 闪速存储器具有包括至少一个块的存储单元阵列，该块具有多个页。 该方法包括接收读取命令以从块中的所选页面读取数据; 确定块是否具有尚未被编程的任何页面; 在确定不被编程的至少一个页面上执行伪数据程序操作; 并且在完成虚拟数据编程操作之后执行读取命令以读取所选择的页面的数据。

公开(公告)号：US07684255B2

公开(公告)日：2010-03-23

申请号：US12119408

申请日：2008-05-12

申请人： You Sung Kim ,  Kwang Jun Cho

发明人： You Sung Kim ,  Kwang Jun Cho

IPC分类号： G11C16/00

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3404

摘要： A method of operating a non-volatile memory device changes a read voltage by determining a degree that threshold voltages of memory cells are changed and overlap each other. The method of operating the non-volatile memory device includes performing a least significant bit (LSB) program of memory cells and determining a first error rate, performing a most significant bit (MSB) program of the memory cells and determining a second error rate, and setting a read voltage corresponding to a value at which the first and second error rates are minimum values.

摘要翻译： 操作非易失性存储器件的方法通过确定存储器单元的阈值电压改变并彼此重叠的程度来改变读取电压。 操作非易失性存储器件的方法包括执行存储器单元的最低有效位（LSB）程序并确定第一错误率，执行存储器单元的最高有效位（MSB）程序并确定第二错误率， 以及设定与第一误差率和第二误差率为最小值的值对应的读取电压。

公开(公告)号：US07660160B2

公开(公告)日：2010-02-09

申请号：US11962060

申请日：2007-12-20

申请人： You Sung Kim ,  Duck Ju Kim

发明人： You Sung Kim ,  Duck Ju Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5642

摘要： A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.

摘要翻译： 公开了一种在闪速存储器件中执行读取操作的方法。 闪速存储器具有包括至少一个块的存储单元阵列，该块具有多个页。 该方法包括接收读取命令以从块中的所选页面读取数据; 确定块是否具有尚未被编程的任何页面; 在确定不被编程的至少一个页面上执行伪数据程序操作; 并且在完成虚拟数据编程操作之后执行读取命令以读取所选择的页面的数据。

公开(公告)号：US07646640B2

公开(公告)日：2010-01-12

申请号：US11951170

申请日：2007-12-05

申请人： Je-Il Ryu ,  You-Sung Kim

发明人： Je-Il Ryu ,  You-Sung Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/08

摘要： A semiconductor memory device includes first and second memory cell blocks, a block decoder, and first and second block switches. The first and second memory cell blocks have a plurality of memory cells connected in a string structure and are respectively disposed in neighboring planes. The block decoder outputs first and second block select signals in response to pre-decoded address signals and first and second plane select signals, which are respectively enabled according to an enable state of the planes. The first and second block switches connect global word lines to word lines of the first and second memory cell blocks in response to the first and second block select signals, respectively.

摘要翻译： 半导体存储器件包括第一和第二存储器单元块，块解码器以及第一和第二块开关。 第一和第二存储单元块具有以串结构连接的多个存储单元，分别设置在相邻的平面中。 块解码器响应于预解码的地址信号和第一和第二平面选择信号输出第一和第二块选择信号，第一和第二平面选择信号分别根据平面的使能状态使能。 响应于第一和第二块选择信号，第一和第二块开关将全局字线连接到第一和第二存储单元块的字线。

公开(公告)号：US07623375B2

公开(公告)日：2009-11-24

申请号：US11966014

申请日：2007-12-28

申请人： You Sung Kim ,  Ji Hye Son

发明人： You Sung Kim ,  Ji Hye Son

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628

摘要： In a method of operating a flash memory device including a memory cell array having a Multi-Level Cell (MLC) for storing plural bit data, a first memory block included in the MLC is selected. First to Mth word lines are selected while increasing from a first column line to an Nth column line, which are included in the first memory block. A lower page of each word line is selected in the order of the word lines. The first to Mth word lines are selected while increasing from the first column line to the Nth column line. An upper page of each word line is selected in the order of the word lines.

摘要翻译： 在包括具有用于存储多位数据的多级单元（MLC）的存储单元阵列的闪速存储器件的方法中，选择包括在MLC中的第一存储块。 从第一列行增加到包括在第一存储器块中的第N列行中，首先选择第M个字行。 以字线的顺序选择每个字线的下页。 当从第一列到第N列行增加时，选择第一至第M字线。 以字线的顺序选择每个字线的上部页面。

公开(公告)号：US20090231916A1

公开(公告)日：2009-09-17

申请号：US12119412

申请日：2008-05-12

申请人： You Sung Kim ,  Jun Rye Rho

发明人： You Sung Kim ,  Jun Rye Rho

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C2211/5641

摘要： A non-volatile memory device increases a number of word lines and a storage capacity using a multi level cell. The non-volatile memory device addresses a problem of self-boosting not being adequately generated due to the increased number of word lines. The non-volatile memory device includes a memory cell array configured to have first memory cells for storing first bit information coupled to third word lines except a first word line adjacent to a drain select line and a second word line adjacent to a source select line, and second memory cells coupled to the first word line and the second word line. The second memory cells store second bit information that is smaller than the first bit information.

摘要翻译： 非易失性存储器件使用多级单元增加字线数量和存储容量。 由于字线数量的增加，非易失性存储器件解决了不能充分产生自增强的问题。 非易失性存储器件包括存储单元阵列，其被配置为具有第一存储器单元，用于存储耦合到第三字线的第一位信息，除了与漏极选择线相邻的第一字线和与源选择线相邻的第二字线， 以及耦合到第一字线和第二字线的第二存储器单元。 第二存储器单元存储小于第一位信息的第二位信息。