Invention Grant
- Patent Title: Apparatus and methods of bit line setup
- Patent Title (中): 位线设置的装置和方法
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Application No.: US13195548Application Date: 2011-08-01
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Publication No.: US08743623B2Publication Date: 2014-06-03
- Inventor: Myung Cho , Seong Je Park , Jung Hwan Lee
- Applicant: Myung Cho , Seong Je Park , Jung Hwan Lee
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/06

Abstract:
Methods and apparatus are disclosed, including an apparatus that has a memory cell array with a memory cell selectively coupled to a bit line. A control circuit is configured to provide a control signal. A voltage generator is configured to provide a sense signal and a precharge signal in response to the control signal. The apparatus further includes a page buffer configured to provide a bit line voltage to the bit line based on the sense signal and the precharge signal, to thereby control a programming of the memory cell.
Public/Granted literature
- US20130033940A1 APPARATUS AND METHODS OF BIT LINE SETUP Public/Granted day:2013-02-07
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