发明授权
- 专利标题: Quad-data rate controller and implementing method thereof
- 专利标题(中): 四数据速率控制器及其实现方法
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申请号: US13496606申请日: 2010-12-22
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公开(公告)号: US08751853B2公开(公告)日: 2014-06-10
- 发明人: Jishan Ding , Wei Huang , Wei Lai , Jianbing Wang , Kedong Yu , Zhiyong Liao
- 申请人: Jishan Ding , Wei Huang , Wei Lai , Jianbing Wang , Kedong Yu , Zhiyong Liao
- 申请人地址: CN Shenzhen, Guangdong Province
- 专利权人: ZTE Corporation
- 当前专利权人: ZTE Corporation
- 当前专利权人地址: CN Shenzhen, Guangdong Province
- 代理机构: Ling and Yang Intellectual Property
- 代理商 Ling Wu; Stephen Yang
- 优先权: CN201010182594 20100521
- 国际申请: PCT/CN2010/080140 WO 20101222
- 国际公布: WO2011/143913 WO 20111124
- 主分类号: G06F1/12
- IPC分类号: G06F1/12
摘要:
A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. The present invention has a shorter delay and does not need any programmable delay element, and is easy to implement.
公开/授权文献
- US20130061083A1 Quad-Data Rate Controller and Realization Method Thereof 公开/授权日:2013-03-07
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