公开(公告)号：US08751853B2

公开(公告)日：2014-06-10

申请号：US13496606

申请日：2010-12-22

申请人： Jishan Ding ,  Wei Huang ,  Wei Lai ,  Jianbing Wang ,  Kedong Yu ,  Zhiyong Liao

发明人： Jishan Ding ,  Wei Huang ,  Wei Lai ,  Jianbing Wang ,  Kedong Yu ,  Zhiyong Liao

IPC分类号： G06F1/12

CPC分类号： G06F13/1689

摘要： A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. The present invention has a shorter delay and does not need any programmable delay element, and is easy to implement.

摘要翻译： 在本发明中公开了四数据速率（QDR）控制器及其实现方法。 该控制器包括：仲裁器，控制状态机，读取数据采样时钟产生模块，读取数据路径模块和读取数据路径校准模块。 仲裁者根据控制状态机的状态对命令和数据进行仲裁; 读数据采样时钟产生模块产生具有相同源和相同频率和不同相位的读数据采样时钟; 读取数据路径校准模块在所生成的读取数据采样时钟中，确定读取数据路径模块的正边缘数据和下降沿数据的采样时钟，以便当控制状态机处于“读取数据路径 校正状态“ 读取数据路径模块根据确定的采样时钟将非系统时钟域中的正沿读取数据和下降沿数据同步到系统时钟域。 本发明具有更短的延迟并且不需要任何可编程延迟元件，并且易于实现。

公开(公告)号：US20130061083A1

公开(公告)日：2013-03-07

申请号：US13496606

申请日：2010-12-22

申请人： Jishan Ding ,  Wei Huang ,  Wei Lai ,  Jianbing Wang ,  Kedong Yu ,  Zhiyong Liao

发明人： Jishan Ding ,  Wei Huang ,  Wei Lai ,  Jianbing Wang ,  Kedong Yu ,  Zhiyong Liao

IPC分类号： G06F1/12

CPC分类号： G06F13/1689

摘要： A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, used to arbitrates commands and data according to the state of the control state machine; a read data sampling clock generating module, used to generate read data sampling clocks with the same source and same frequency and different phases; a read data path calibrating module, used to determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; a read data path module, used to synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks.

摘要翻译： 在本发明中公开了四数据速率（QDR）控制器及其实现方法。 控制器包括：仲裁器，用于根据控制状态机的状态仲裁命令和数据; 读取数据采样时钟产生模块，用于产生具有相同源和相同频率和不同相位的读取数据采样时钟; 读取数据路径校准模块，用于在所生成的读取数据采样时钟中确定正边沿数据的采样时钟和读取数据路径模块的下降沿数据，以便在读取控制状态机时通过读取训练词来读取数据 数据路径校准状态; 读取数据路径模块，用于根据确定的采样时钟将非边缘读取数据和非系统时钟域中的下降沿数据同步到系统时钟域。