发明授权
- 专利标题: Semiconductor wafer and laminate structure including the same
- 专利标题(中): 半导体晶片和包括其的层压结构
-
申请号: US13365516申请日: 2012-02-03
-
公开(公告)号: US08766407B2公开(公告)日: 2014-07-01
- 发明人: Mitsuyoshi Endo
- 申请人: Mitsuyoshi Endo
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权: JP2011-189390 20110831
- 主分类号: H01L29/06
- IPC分类号: H01L29/06
摘要:
According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.
公开/授权文献
信息查询
IPC分类: