Invention Grant
- Patent Title: Integrated circuit including interconnect levels
- Patent Title (中): 集成电路包括互连级别
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Application No.: US13739389Application Date: 2013-01-11
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Publication No.: US08766444B2Publication Date: 2014-07-01
- Inventor: Herbert Gietler , Gerhard Zojer , Benjamin Finke
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.
Public/Granted literature
- US20130127066A1 Integrated Circuit Including Interconnect Levels Public/Granted day:2013-05-23
Information query
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