发明授权
US08769374B2 Multi-write endurance and error control coding of non-volatile memories
有权
非易失性存储器的多写耐力和错误控制编码
- 专利标题: Multi-write endurance and error control coding of non-volatile memories
- 专利标题(中): 非易失性存储器的多写耐力和错误控制编码
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申请号: US12903695申请日: 2010-10-13
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公开(公告)号: US08769374B2公开(公告)日: 2014-07-01
- 发明人: Michele M. Franceschini , Ashish Jagmohan
- 申请人: Michele M. Franceschini , Ashish Jagmohan
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Cantor Colburn LLP
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page.
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