发明授权
- 专利标题: Semiconductor interconnect structures
- 专利标题(中): 半导体互连结构
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申请号: US13693598申请日: 2012-12-04
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公开(公告)号: US08772938B2公开(公告)日: 2014-07-08
- 发明人: Boyan Boyanov , Kanwal Singh , James Clarke , Alan Myers
- 申请人: Boyan Boyanov , Kanwal Singh , James Clarke , Alan Myers
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Finch & Maloney PLLC
- 主分类号: H01L21/3205
- IPC分类号: H01L21/3205
摘要:
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
公开/授权文献
- US20140151893A1 SEMICONDUCTOR INTERCONNECT STRUCTURES 公开/授权日:2014-06-05
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