发明授权
US08779553B2 Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone
有权
用于集成电路的应力感知设计，包括应力诱导结构和保持区域
- 专利标题： Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone
- 专利标题（中）： 用于集成电路的应力感知设计，包括应力诱导结构和保持区域
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申请号： US13162541申请日： 2011-06-16
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公开(公告)号： US08779553B2公开(公告)日： 2014-07-15
- 发明人: Arifur Rahman
- 申请人： Arifur Rahman
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 Kevin T. Cuenot
- 主分类号： H01L29/06
- IPC分类号： H01L29/06
摘要：
A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.
公开/授权文献
- US20120319248A1 STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS 公开/授权日：2012-12-20