Invention Grant
US08782586B2 Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning
有权
用于布线要通过双重图案化制造的集成电路的方法，系统和程序产品
- Patent Title: Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning
- Patent Title (中): 用于布线要通过双重图案化制造的集成电路的方法，系统和程序产品
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Application No.: US12582366Application Date: 2009-10-20
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Publication No.: US08782586B2Publication Date: 2014-07-15
- Inventor: Abdurrahman Sezginer , David Cooke Noice , Jason Sweis , Vassilios Gerousis , Sozen Yao
- Applicant: Abdurrahman Sezginer , David Cooke Noice , Jason Sweis , Vassilios Gerousis , Sozen Yao
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.
Public/Granted literature
Information query
