发明授权
- 专利标题: Wafer level packaging using a lead-frame
- 专利标题(中): 晶圆级封装采用引线框架
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申请号: US13689416申请日: 2012-11-29
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公开(公告)号: US08785244B2公开(公告)日: 2014-07-22
- 发明人: Ahmad R. Ashrafzadeh
- 申请人: Ahmad R. Ashrafzadeh
- 申请人地址: US CA San Jose
- 专利权人: Maxim Integrated Products, Inc.
- 当前专利权人: Maxim Integrated Products, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Blakely Sokoloff Taylor & Zafman LLP
- 主分类号: H01L21/56
- IPC分类号: H01L21/56
摘要:
Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.
公开/授权文献
- US20130089951A1 Wafer Level Packaging Using a Lead-Frame 公开/授权日:2013-04-11
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