公开(公告)号：US08785248B2

公开(公告)日：2014-07-22

申请号：US13346443

申请日：2012-01-09

申请人： Ahmad R. Ashrafzadeh

发明人： Ahmad R. Ashrafzadeh

IPC分类号： H01L21/98

CPC分类号： H01L23/3114 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00

摘要： Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.

公开(公告)号：US06369559B1

公开(公告)日：2002-04-09

申请号：US09713582

申请日：2000-11-15

申请人： Ahmad R. Ashrafzadeh

发明人： Ahmad R. Ashrafzadeh

IPC分类号： G05F140

CPC分类号： H02M3/158 ,  H02M2001/009

摘要： A DC converter to connect a first DC voltage to a second DC voltage includes a first switch connected to input the first DC voltage, a second switch connected to the first switch, the first switch and the second switch generating a first main voltage, a third switch connected to the first switch, a fourth switch connected to the third switch, and a latch circuit to control the third switch and to control the fourth switch.

摘要翻译： 将第一DC电压连接到第二DC电压的DC转换器包括连接到第一DC电压的第一开关，连接到第一开关的第二开关，第一开关和产生第一主电压的第二开关，第三开关 连接到第一开关的开关，连接到第三开关的第四开关，以及用于控制第三开关并控制第四开关的锁存电路。

公开(公告)号：US20130089951A1

公开(公告)日：2013-04-11

申请号：US13689416

申请日：2012-11-29

申请人： Ahmad R. Ashrafzadeh

发明人： Ahmad R. Ashrafzadeh

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.

公开(公告)号：US09367502B1

公开(公告)日：2016-06-14

申请号：US13481313

申请日：2012-05-25

申请人： Ahmad R. Ashrafzadeh

发明人： Ahmad R. Ashrafzadeh

IPC分类号： G06F13/42 ,  H04B1/38 ,  H04L5/16 ,  B23K11/24 ,  H02B1/24 ,  G06F13/38 ,  H04B1/40

CPC分类号： G06F13/385 ,  H04B1/40

摘要： Communication methods and apparatus and power supply controllers using the same. The method includes transferring information over a line from a first location to a second location as a voltage signal while simultaneously transferring information over the same line from the second location to the first location as a current signal. Further, digital information may be transmitted over the same line. When applied to a power supply controller system, a master controller may control a plurality of slave controllers by initially setting up the slave controllers by transmitting digital information to the slave controllers, and then maintaining a set point for each controller while monitoring controller characteristics over the same lines.

摘要翻译： 通信方法和设备及使用其的电源控制器。 该方法包括通过线路将信息从第一位置传送到第二位置作为电压信号，同时将信息从同一行从第二位置传送到第一位置作为当前信号。 此外，数字信息可以在同一行上传输。 当应用于电源控制器系统时，主控制器可以通过初始设置从控制器来控制多个从控制器，通过将数字信息发送到从控制器，然后保持每个控制器的设定点，同时监视控制器的特性 相同的行。

公开(公告)号：US08785244B2

公开(公告)日：2014-07-22

申请号：US13689416

申请日：2012-11-29

申请人： Ahmad R. Ashrafzadeh

发明人： Ahmad R. Ashrafzadeh

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.

摘要翻译： 晶圆级封装采用引线框架。 当用于封装两个或更多个芯片时，最终产品具有QFN封装形状。 由于两个或更多个芯片的连接非常紧密，并且每个芯片的制造处理只能达到该芯片上的器件所需的能力，因此最终产品的性能将会相当于或超过对应的单片芯片。 。 晶片级封装还可用于封装单片芯片，以及在一个芯片上具有有源器件的芯片和第二芯片上的无源器件。 公开了各种示例性实施例。

公开(公告)号：US20130089953A1

公开(公告)日：2013-04-11

申请号：US13346443

申请日：2012-01-09

申请人： Ahmad R. Ashrafzadeh

发明人： Ahmad R. Ashrafzadeh

IPC分类号： H01L21/98

CPC分类号： H01L23/3114 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00

摘要： Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.

摘要翻译： 晶圆级封装采用引线框架。 当用于封装两个或更多个芯片时，最终产品具有QFN封装形状。 由于两个或更多个芯片的连接非常紧密，并且每个芯片的制造处理只能达到该芯片上的器件所需的最终产品，因此最终产品的性能可能与对应的单片芯片的性能相当甚至超过相应的单片芯片。 。 晶片级封装还可用于封装单片芯片，以及在一个芯片上具有有源器件的芯片和第二芯片上的无源器件。 公开了各种示例性实施例。

公开(公告)号：US20100072615A1

公开(公告)日：2010-03-25

申请号：US12237078

申请日：2008-09-24

申请人： Arkadii V. Samoilov ,  Duane Thomas Wilcoxen ,  Viren V. Khandekar ,  Vivek Jain ,  Ahmad R. Ashrafzadeh ,  Mansour Izadinia

发明人： Arkadii V. Samoilov ,  Duane Thomas Wilcoxen ,  Viren V. Khandekar ,  Vivek Jain ,  Ahmad R. Ashrafzadeh ,  Mansour Izadinia

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05553 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

摘要： The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer.

摘要翻译： 本发明涉及晶片级封装芯片级焊盘安装集成电路的载流能力最大化的各个方面。 在一个方面，通过使用矩形焊盘彼此间隔的方式将焊盘区域最大化，因为可靠地安装到电路板将允许焊盘区域。 在另一方面，可以使用多个接触焊盘来增加电流容量而不使用不同区域的接触焊盘。 在另一方面，通孔用于将高电流分​​量或组分的一个引线直接连接到该组件正上方的接触焊盘，并且通过厚金属将高电流分​​量的第二引线布线到相邻的接触焊盘 互连层。