Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal. An interpolation circuit receives the first and second voltages, selected by the decoder, to output a voltage level obtained on interpolation with an interpolation ratio of 1:1 (FIG. 1).