Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.