Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the silicon-on-insulator area down to a buried oxide layer on which the silicon-on-insulator layer is formed. The position of the trench is self-aligned and defined by the gate width and the dimension of spacers disposed on either side of the gate. The isolation trench is filled with a dielectric material and then etched back to the middle of the SOI body and the remaining volume is filled with a doped conductive material. The doped conductor is subject to a thermal cycle to create source and drain regions of the device through out-diffusion of the doped material.