Invention Grant
- Patent Title: Display and automatic improvement of timing and area in a network-on-chip
- Patent Title (中): 显示和自动改进片上网络的时序和面积
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Application No.: US13487087Application Date: 2012-06-01
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Publication No.: US08793644B2Publication Date: 2014-07-29
- Inventor: Daniel Michel , Xavier Van Ruymbeke , Pascal Godet , Xavier Leloup
- Applicant: Daniel Michel , Xavier Van Ruymbeke , Pascal Godet , Xavier Leloup
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Technologies, Inc.
- Current Assignee: Qualcomm Technologies, Inc.
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.
Public/Granted literature
- US20120311512A1 Display and automatic improvement of timing and area in a network-on-chip Public/Granted day:2012-12-06
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