公开(公告)号：US08793644B2

公开(公告)日：2014-07-29

申请号：US13487087

申请日：2012-06-01

Applicant: Daniel Michel ,  Xavier Van Ruymbeke ,  Pascal Godet ,  Xavier Leloup

Inventor： Daniel Michel ,  Xavier Van Ruymbeke ,  Pascal Godet ,  Xavier Leloup

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/505 ,  G06F2217/84

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract translation: 公开了一种方法和NoC设计工具，其将定时报告中列出的路径和区域报告中的单位大小自动映射到NoC的拓扑，并在GUI中显示路径和单位大小。 该工具还可以自动添加流水线阶段，由时间预算允许的最大延迟分隔，以便以自动方式实现时序收敛。

公开(公告)号：US20120311512A1

公开(公告)日：2012-12-06

申请号：US13487087

申请日：2012-06-01

Applicant: Daniel Michel ,  Xavier Van Ruymbeke ,  Pascal Godet ,  Xavier Leloup

Inventor： Daniel Michel ,  Xavier Van Ruymbeke ,  Pascal Godet ,  Xavier Leloup

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/505 ,  G06F2217/84

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract translation: 公开了一种方法和NoC设计工具，其将定时报告中列出的路径和区域报告中的单位大小自动映射到NoC的拓扑，并在GUI中显示路径和单位大小。 该工具还可以自动添加流水线阶段，由时间预算允许的最大延迟分隔，以便以自动方式实现时序收敛。

公开(公告)号：US07755920B2

公开(公告)日：2010-07-13

申请号：US12284820

申请日：2008-09-25

Applicant: Philippe Boucard ,  Pascal Godet ,  Luc Montperrus

Inventor： Philippe Boucard ,  Pascal Godet ,  Luc Montperrus

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00

CPC classification number: G11C7/1039 ,  G06F12/0893 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C2207/104 ,  G11C2207/2245

Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Abstract translation: 一种电子存储装置，包括设置有高速缓冲存储器的一组存储器，用于提供对所述存储器组的物理存取的定序器，用于接收高级存储器访问请求的物理接口，物理接口和定序器之间的请求管理器，所述请求 管理器包括用于存储高级存储器访问请求的输入队列和考虑高速缓存的数据和输入队列的数据以指定要执行的请求的仲裁功能，从而允许存储体， 定序器和请求管理器在单个芯片上提供，物理接口提供芯片与外部的连接。

公开(公告)号：US20090080280A1

公开(公告)日：2009-03-26

申请号：US12284820

申请日：2008-09-25

Applicant: Philippe Boucard ,  Pascal Godet ,  Luc Montperrus

Inventor： Philippe Boucard ,  Pascal Godet ,  Luc Montperrus

IPC: G11C8/00

CPC classification number: G11C7/1039 ,  G06F12/0893 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C2207/104 ,  G11C2207/2245

Abstract: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Abstract translation: 一种电子存储装置，包括设置有高速缓冲存储器的一组存储器，用于提供对所述存储器组的物理存取的定序器，用于接收高级存储器访问请求的物理接口，物理接口和定序器之间的请求管理器，所述请求 管理器包括用于存储高级存储器访问请求的输入队列和考虑高速缓存的数据和输入队列的数据以指定要执行的请求的仲裁功能，从而允许存储体， 定序器和请求管理器在单个芯片上提供，物理接口提供芯片与外部的连接。