Invention Grant
- Patent Title: Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
- Patent Title (中): 半导体晶圆的三维集成电路结构和混合键合方法
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Application No.: US13488745Application Date: 2012-06-05
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Publication No.: US08809123B2Publication Date: 2014-08-19
- Inventor: Ping-Yin Liu , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
- Applicant: Ping-Yin Liu , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.
Public/Granted literature
- US20130320556A1 Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers Public/Granted day:2013-12-05
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