公开(公告)号：US10553785B2

公开(公告)日：2020-02-04

申请号：US13452230

申请日：2012-04-20

申请人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

摘要： This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

公开(公告)号：US09054121B2

公开(公告)日：2015-06-09

申请号：US13280075

申请日：2011-10-24

申请人： Ping-Yin Liu ,  Xin-Hua Huang ,  Hsin-Ting Huang ,  Yuan-Chih Hsieh ,  Jung-Huei Peng ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Chun-Wen Cheng

发明人： Ping-Yin Liu ,  Xin-Hua Huang ,  Hsin-Ting Huang ,  Yuan-Chih Hsieh ,  Jung-Huei Peng ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Chun-Wen Cheng

IPC分类号： H01L21/31 ,  H01L49/02 ,  B81C1/00 ,  H01G5/16

CPC分类号： B81B7/0058 ,  B81B3/0005 ,  B81B3/0021 ,  B81C1/00269 ,  B81C1/00793 ,  B81C2201/053 ,  B81C2203/0109 ,  H01G5/16 ,  H01L28/60

摘要： A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.

摘要翻译： 一种方法包括形成MEMS器件，形成与MEMS器件相邻的接合层，并在接合层上形成保护层。 形成接合层和保护层的步骤包括接合层和保护层的原位沉积。

公开(公告)号：US08945344B2

公开(公告)日：2015-02-03

申请号：US13554751

申请日：2012-07-20

申请人： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： B32B38/10

CPC分类号： H01L21/67092 ,  Y10T156/11 ,  Y10T156/1132 ,  Y10T156/1153 ,  Y10T156/1189 ,  Y10T156/1911 ,  Y10T156/1944 ,  Y10T156/1972

摘要： Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.

摘要翻译： 公开了分离键合晶片的系统和方法。 在一个实施例中，用于分离接合的晶片的系统包括用于接合的晶片的支撑件和用于向结合的晶片施加纯粹的力的装置。 该系统还包括用于向接合晶片施加真空的装置。

公开(公告)号：US08846129B2

公开(公告)日：2014-09-30

申请号：US13372141

申请日：2012-02-13

申请人： Hung-Hua Lin ,  Li-Cheng Chu ,  Ming-Tung Wu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Hung-Hua Lin ,  Li-Cheng Chu ,  Ming-Tung Wu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： B05D3/10 ,  C12Q1/68 ,  H01L21/311

CPC分类号： G01N21/55 ,  G01N21/01 ,  G01N21/253 ,  G01N27/327 ,  G01N33/483 ,  G01N2021/0106 ,  G01N2201/0636

摘要： A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.

摘要翻译： 形成包括衬底的一部分的生物感测结构的方法被凹进以在衬底中形成多个台面。 多个台面中的每一个具有顶表面和侧壁表面。 第一光反射层沉积在每个台面的顶表面和侧壁表面上。 在第一光反射层的第一部分上形成填充材料。 沉积在填充材料上的停止层和第一光反射层的第二部分。 牺牲层形成在停止层上并且被平坦化地暴露停止层。 在停止层和第一光反射层中形成第一开口。 第二光反射层沉积在第一开口上。 在第二光反射层中形成第二开口。

公开(公告)号：US08809123B2

公开(公告)日：2014-08-19

申请号：US13488745

申请日：2012-06-05

申请人： Ping-Yin Liu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Ping-Yin Liu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/08147 ,  H01L2224/08502 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80204 ,  H01L2224/80345 ,  H01L2224/80805 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2224/05552

摘要： Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.

摘要翻译： 公开了用于半导体晶片的三维集成电路（3DIC）结构和混合键合方法。 3DIC结构包括第一半导体器件，其第一导电焊盘设置在其顶表面上的第一绝缘材料内，第一导电焊盘在其顶表面上具有第一凹部。 3DIC结构包括第二半导体器件，其第二导电焊盘设置在耦合到第一半导体器件的顶表面上的第二绝缘材料内，第二导电焊盘在其顶表面上具有第二凹槽。 密封层设置在第一导电垫和第一凹槽和第二凹槽中的第二导电垫之间。 密封层将第一导电焊盘连接到第二导电焊盘。 第一绝缘材料结合到第二绝缘材料上。

公开(公告)号：US20140020818A1

公开(公告)日：2014-01-23

申请号：US13554751

申请日：2012-07-20

申请人： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： B32B38/10 ,  B32B37/02

CPC分类号： H01L21/67092 ,  Y10T156/11 ,  Y10T156/1132 ,  Y10T156/1153 ,  Y10T156/1189 ,  Y10T156/1911 ,  Y10T156/1944 ,  Y10T156/1972

摘要： Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.

摘要翻译： 公开了分离键合晶片的系统和方法。 在一个实施例中，用于分离接合的晶片的系统包括用于接合的晶片的支撑件和用于向结合的晶片施加纯粹的力的装置。 该系统还包括用于向接合晶片施加真空的装置。

公开(公告)号：US08629531B2

公开(公告)日：2014-01-14

申请号：US13030645

申请日：2011-02-18

申请人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

公开(公告)号：US20140011324A1

公开(公告)日：2014-01-09

申请号：US13542507

申请日：2012-07-05

申请人： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21/50

CPC分类号： H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

摘要： Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

摘要翻译： 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

公开(公告)号：US08598687B2

公开(公告)日：2013-12-03

申请号：US13481574

申请日：2012-05-25

申请人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

发明人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC分类号： H01L29/40

CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

公开(公告)号：US08569849B2

公开(公告)日：2013-10-29

申请号：US13618908

申请日：2012-09-14

申请人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

发明人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  G11C11/16

摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

摘要翻译： 提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。 顶部电极可以具有倾斜的侧壁。 可以通过沉积相应的MTJ层来形成MTJ堆叠。 可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。 开口填充有导电材料以形成顶部电极。 然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。