Invention Grant
US08810018B2 Stacked integrated circuit package system with face to face stack configuration
有权
堆叠集成电路封装系统,具有面对面堆叠配置
- Patent Title: Stacked integrated circuit package system with face to face stack configuration
- Patent Title (中): 堆叠集成电路封装系统,具有面对面堆叠配置
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Application No.: US11307382Application Date: 2006-02-03
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Publication No.: US08810018B2Publication Date: 2014-08-19
- Inventor: Jong-Woo Ha , Sang-Ho Lee , Soo-San Park
- Applicant: Jong-Woo Ha , Sang-Ho Lee , Soo-San Park
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A stacked integrated circuit package system is provided forming a first molded chip comprises attaching a conductor on a wafer, applying an encapsulant around the conductor, and exposing a surface of the conductor in the encapsulant, attaching a first electrical interconnect on the conductor of the first molded chip and stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.
Public/Granted literature
- US20070181998A1 STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FACE TO FACE STACK CONFIGURATION Public/Granted day:2007-08-09
Information query
IPC分类: