Invention Grant
- Patent Title: Interconnect structure for wafer level package
- Patent Title (中): 晶圆级封装的互连结构
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Application No.: US13170973Application Date: 2011-06-28
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Publication No.: US08829676B2Publication Date: 2014-09-09
- Inventor: Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng
- Applicant: Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L23/485
- IPC: H01L23/485

Abstract:
A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
Public/Granted literature
- US20130001776A1 Interconnect Structure for Wafer Level Package Public/Granted day:2013-01-03
Information query
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