Invention Grant
US08837234B2 Voltage control method to minimize a coupling noise between adjacent global bit lines during read-while operation and memory device using the same
有权
电压控制方法，用于在读操作期间使相邻全局位线之间的耦合噪声最小化，以及使用该耦合噪声的存储器件
- Patent Title: Voltage control method to minimize a coupling noise between adjacent global bit lines during read-while operation and memory device using the same
- Patent Title (中): 电压控制方法，用于在读操作期间使相邻全局位线之间的耦合噪声最小化，以及使用该耦合噪声的存储器件
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Application No.: US13209010Application Date: 2011-08-12
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Publication No.: US08837234B2Publication Date: 2014-09-16
- Inventor: Yu Hwan Ro , Beak Hyung Cho , Ki Whan Song , Young Don Choi
- Applicant: Yu Hwan Ro , Beak Hyung Cho , Ki Whan Song , Young Don Choi
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2010-0078098 20100813
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/4094 ; G11C7/02 ; G11C7/10 ; G11C7/12 ; G11C7/18 ; G11C11/4097
Abstract:
A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.
Public/Granted literature
- US20120039141A1 VOLTAGE CONTROL METHOD AND MEMORY DEVICE USING THE SAME Public/Granted day:2012-02-16
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