发明授权
US08838057B2 Harmonic rejection mixer architecture with reduced sensitivity to gain and phase mismatches 有权
谐波抑制混频器架构,增益和相位不匹配的灵敏度降低

Harmonic rejection mixer architecture with reduced sensitivity to gain and phase mismatches
摘要:
A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.
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