Harmonic Rejection Mixer Architecture with Reduced Sensitivity to Gain and Phase Mismatches
    1.
    发明申请
    Harmonic Rejection Mixer Architecture with Reduced Sensitivity to Gain and Phase Mismatches 有权
    谐波抑制混频器架构,增益和相位不匹配灵敏度降低

    公开(公告)号:US20120322398A1

    公开(公告)日:2012-12-20

    申请号:US13331792

    申请日:2011-12-20

    IPC分类号: H04B1/10

    摘要: A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.

    摘要翻译: 谐波抑制混频器包括用于缩放RF信号以产生多个缩放的RF信号的第一缩放电路,用于使用第一多个开关信号对缩放的RF信号进行采样的第一开关级,以及用于混合采样的第二混频阶段 具有第二多个开关信号的RF信号以产生具有不同相位的多个频率转换信号。 组合器将频率转换的信号加在一起以产生RF信号的第一多个基带版本。 第一放大器级处理第一多个基带版本以产生第二多个基带版本。 混频器还包括用于缩放第二多个基带版本的第二缩放电路和第二放大器级,以从缩放的第二多个基带版本生成同相基带信号和正交基带信号。

    Harmonic rejection mixer architecture with reduced sensitivity to gain and phase mismatches
    2.
    发明授权
    Harmonic rejection mixer architecture with reduced sensitivity to gain and phase mismatches 有权
    谐波抑制混频器架构,增益和相位不匹配的灵敏度降低

    公开(公告)号:US08838057B2

    公开(公告)日:2014-09-16

    申请号:US13331792

    申请日:2011-12-20

    IPC分类号: H04B1/10 H03D7/16 H03D7/14

    摘要: A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.

    摘要翻译: 谐波抑制混频器包括用于缩放RF信号以产生多个缩放的RF信号的第一缩放电路,用于使用第一多个开关信号对缩放的RF信号进行采样的第一开关级,以及用于混合采样的第二混频阶段 具有第二多个开关信号的RF信号以产生具有不同相位的多个频率转换信号。 组合器将频率转换的信号加在一起以产生RF信号的第一多个基带版本。 第一放大器级处理第一多个基带版本以产生第二多个基带版本。 混频器还包括用于缩放第二多个基带版本的第二缩放电路和第二放大器级,以从缩放的第二多个基带版本生成同相基带信号和正交基带信号。

    Multi-layer time-interleaved analog-to-digital convertor (ADC)
    3.
    发明授权
    Multi-layer time-interleaved analog-to-digital convertor (ADC) 有权
    多层时间交织模数转换器(ADC)

    公开(公告)号:US08611483B2

    公开(公告)日:2013-12-17

    申请号:US13485003

    申请日:2012-05-31

    IPC分类号: H04B1/10 H04K3/00

    摘要: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

    摘要翻译: 射频(RF)接收机可以包括第一采样模块,其可操作以特定主采样率的第一电平采样; 多个第二级采样模块,其中所述多个第二级采样模块中的每一个可操作以以与主采样速率相比减小的第二采样速率在第二电平中采样第一电平的输出 ; 以及多个第三级模块,每个模块包括多个第三级采样子模块,所述第三级采样子模块可操作以以与第二采样速率相比减小的第三采样率进行采样,以及多个相应的模拟 - 数字转换(ADC)子模块。

    Input matching circuit for multiband low noise amplifier
    4.
    发明申请
    Input matching circuit for multiband low noise amplifier 失效
    多频低噪声放大器输入匹配电路

    公开(公告)号:US20050225397A1

    公开(公告)日:2005-10-13

    申请号:US11088591

    申请日:2005-03-24

    摘要: Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.

    摘要翻译: 提供了一种包括第一晶体管,输入匹配电路和第一电容器的多频带低噪声放大器。 第一晶体管包括电连接到第一电源,接地发射极和与第一电感器的另一端连接的基极的集电极,第一电感器的一端作为低噪声放大器的输入端。 输入匹配电路连接在第一晶体管的集电极和基极之间。 第一个电容连接到第一个transistior的收集器。 输入匹配电路包括变容二极管。 输入匹配电路包括连接到变容二极管的第二电容器。 输入匹配电路包括连接到变容二极管的第一电阻器。 在多频带低噪声放大器中,具有可变电容的变容二极管安装在输入端,从而通过少量的偏置电压控制容易地执行频带切换并且最小化可能由控制信号引起的噪声。

    MULTI-LAYER TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTOR (ADC)
    5.
    发明申请
    MULTI-LAYER TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTOR (ADC) 有权
    多层时间间隔模数转换器(ADC)

    公开(公告)号:US20120309337A1

    公开(公告)日:2012-12-06

    申请号:US13485003

    申请日:2012-05-31

    IPC分类号: H03M1/12 H04B1/16

    摘要: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

    摘要翻译: 射频(RF)接收机可以包括第一采样模块,其可操作以特定主采样率的第一电平采样; 多个第二级采样模块,其中所述多个第二级采样模块中的每一个可操作以以与主采样速率相比减小的第二采样速率在第二电平中采样第一电平的输出 ; 以及多个第三级模块,每个模块包括多个第三级采样子模块,所述第三级采样子模块可操作以以与第二采样速率相比减小的第三采样率进行采样,以及多个相应的模拟 - 数字转换(ADC)子模块。

    Input matching circuit for multiband low noise amplifier
    6.
    发明授权
    Input matching circuit for multiband low noise amplifier 失效
    多频低噪声放大器输入匹配电路

    公开(公告)号:US07253688B2

    公开(公告)日:2007-08-07

    申请号:US11088591

    申请日:2005-03-24

    IPC分类号: H03F3/191 H03F1/22

    摘要: Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.

    摘要翻译: 提供了一种包括第一晶体管,输入匹配电路和第一电容器的多频带低噪声放大器。 第一晶体管包括电连接到第一电源,接地发射极和与第一电感器的另一端连接的基极的集电极,第一电感器的一端作为低噪声放大器的输入端。 输入匹配电路连接在第一晶体管的集电极和基极之间。 第一个电容连接到第一个transistior的收集器。 输入匹配电路包括变容二极管。 输入匹配电路包括连接到变容二极管的第二电容器。 输入匹配电路包括连接到变容二极管的第一电阻器。 在多频带低噪声放大器中,具有可变电容的变容二极管安装在输入端,从而通过少量的偏置电压控制容易地执行频带切换并且最小化可能由控制信号引起的噪声。