发明授权
US08838661B2 Radix-8 fixed-point FFT logic circuit characterized by preservation of square root-i operation
有权
特点是保存平方根i操作的基数为8的定点FFT逻辑电路
- 专利标题: Radix-8 fixed-point FFT logic circuit characterized by preservation of square root-i operation
- 专利标题(中): 特点是保存平方根i操作的基数为8的定点FFT逻辑电路
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申请号: US13300710申请日: 2011-11-21
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公开(公告)号: US08838661B2公开(公告)日: 2014-09-16
- 发明人: Yasunao Katayama , Kohji Takano
- 申请人: Yasunao Katayama , Kohji Takano
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Jeff Tang
- 优先权: JP2010-272947 20101207
- 主分类号: G06F17/14
- IPC分类号: G06F17/14
摘要:
A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.
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