CONTROL AND MONITORING FOR FAST MILLIMETER-WAVE LINK USING OUT-OF-BAND WIRELESS CHANNEL
    1.
    发明申请
    CONTROL AND MONITORING FOR FAST MILLIMETER-WAVE LINK USING OUT-OF-BAND WIRELESS CHANNEL 失效
    使用带外无线通道的快速毫米波链路的控制和监控

    公开(公告)号:US20120210167A1

    公开(公告)日:2012-08-16

    申请号:US13371560

    申请日:2012-02-13

    IPC分类号: G06F11/14 H04W24/00

    摘要: A method for fast and efficient data downloading in wireless communications. The method includes ways to download file data of a large size from a server (access point) to a user's client (mobile device) at high speed and efficiency by using both mmWave wireless communication and conventional wireless communication (WiFi, 3G, etc.). A server transmits packetized file data to a client. The file data is transmitted as data packets via mmWave. In parallel, the server transmits check packets (roll-call packets) corresponding to the data packets. As a test at the time of establishing links, the latency for each communication line is measured. The receiver side, upon completion of receiving the check packets, checks whether their corresponding mmWave packets have arrived. If any corresponding mmWave packet has not arrived, it is determined that the mmWave packet has been lost and a retransmission request is immediately returned to the server via WiFi.

    摘要翻译: 一种无线通信中快速有效的数据下载方法。 该方法包括通过使用毫米波无线通信和常规无线通信(WiFi,3G等),以高速和高效的方式将大尺寸的文件数据从服务器(接入点)下载到用户的客户端(移动设备) 。 服务器将打包的文件数据发送给客户机。 文件数据通过mmWave作为数据包传输。 并行地,服务器发送对应于数据分组的检查分组(roll-call packet)。 作为建立链路时的测试,测量每条通信线路的延迟。 接收方在接收到检查数据包完成后,检查其对应的mmWave数据包是否到达。 如果没有到达任何相应的mmWave分组,则确定mmWave分组已经丢失,并且通过WiFi立即将重传请求返回给服务器。

    Multiplier and cipher circuit
    2.
    发明授权
    Multiplier and cipher circuit 失效
    乘法器和加密电路

    公开(公告)号:US08244790B2

    公开(公告)日:2012-08-14

    申请号:US10762174

    申请日:2004-01-21

    IPC分类号: G06F7/52

    摘要: A multiplier circuit is disclosed including a Wallace tree block and a carry propagation adder. The Wallace tree block includes a sum calculation block adding partial products for each digit and a carry calculation block adding carries obtained in the addition by the sum calculation block. In the case of multiplication over an extension field (finite field GF(2n)) of two, a result of calculation by the sum calculation block is outputted. The carry propagation adder adds the result of calculation by the sum calculation block and a result of calculation by the carry calculation block. In the case of multiplication for integers (finite field GF(p)), a result of calculation by the carry propagation adder is outputted.

    摘要翻译: 公开了一种包括华莱士树块和进位传播加法器的乘法器电路。 华莱士树块包括对每个数字加上部分乘积的和计算块,以及通过和计算块在加法中获得的携带运算块。 在扩展字段(有限域GF(2n))乘以2的情况下,输出由和计算块计算的结果。 进位传播加法器将和计算块的计算结果和进位计算块的计算结果相加。 在对于整数乘法(有限域GF(p))的情况下,输出由进位传播加法器计算的结果。

    Method and apparatus for obtaining trace information of multiple processors on an SoC using a segmented trace ring bus to enable a flexible trace output configuration
    3.
    发明授权
    Method and apparatus for obtaining trace information of multiple processors on an SoC using a segmented trace ring bus to enable a flexible trace output configuration 有权
    使用分段跟踪环总线在SoC上获取多个处理器的跟踪信息以实现灵活的跟踪输出配置的方法和装置

    公开(公告)号:US07743199B2

    公开(公告)日:2010-06-22

    申请号:US12108158

    申请日:2008-04-23

    IPC分类号: G06F13/00 G01R31/28

    CPC分类号: G06F11/349 G06F11/3485

    摘要: An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment. Each trace output circuit is configured to transmit trace information to a respective peripheral I/O channel when in the enabled state. Each trace output circuit is configured to transmit trace information to the adjacent downstream segment when in the disabled state.

    摘要翻译: 用于从包括在具有一个或多个外设I / O通道的集成芯片上的多个处理器发送跟踪信息的集成总线架构包括分段总线,其具有以环形拓扑布置的多个段,并且被配置为以圆形方式传送跟踪信息 路径从上游段到下游段,以及一个或多个跟踪输出电路,每个跟踪输出电路各自连接到相应的段,并且每个跟踪输出电路都包括被配置为在启用和禁用状态之间动态切换的交换机 多个段包括用于每个处理器的相应段,其具有连接到处理器的跟踪端口的耦合单元。 耦合单元被配置为从跟踪端口接收跟踪信息,以从相邻的上游段接收跟踪信息,并将跟踪信息的项目发送到相邻的下游段。 每个跟踪输出电路被配置为当处于使能状态时将跟踪信息发送到相应的外设I / O通道。 每个跟踪输出电路被配置为当处于禁用状态时将跟踪信息发送到相邻的下游段。

    OBSERVATION APPARATUS, OBSERVATION METHOD AND PROGRAM
    4.
    发明申请
    OBSERVATION APPARATUS, OBSERVATION METHOD AND PROGRAM 有权
    观察装置,观察方法和程序

    公开(公告)号:US20070203675A1

    公开(公告)日:2007-08-30

    申请号:US11680542

    申请日:2007-02-28

    IPC分类号: G06F15/00

    CPC分类号: G01R31/31704

    摘要: An observation apparatus which observers operations of an observation target apparatus, and which includes: an output signal acquisition unit for sequentially acquiring signal values by observing signals outputted by the observation target apparatus; a state storage unit for sequentially storing the acquired signal values; a determination unit for determining whether a first signal value newly acquired is identical with a second signal value which is acquired prior to the first signal value, and which is stored in the state storage unit; and a separation unit for separating and outputting a signal sequence, which includes a plurality of signal values acquired between the first signal value and the second signal value, as transactions of the output signals, on condition that it is determined that the first signal value is identical with the second signal value.

    摘要翻译: 观察观察对象装置的观察装置,其特征在于,包括:输出信号获取部,其通过观察观察对象装置输出的信号顺次取得信号值; 状态存储单元,用于顺序地存储所获取的信号值; 确定单元,用于确定新获取的第一信号值是否与在所述第一信号值之前获取的第二信号值相同,并且被存储在所述状态存储单元中; 以及分离单元,用于在确定所述第一信号值为(否)的情况下,分离并输出包括在所述第一信号值和所述第二信号值之间获取的多个信号值的信号序列作为所述输出信号的交易; 与第二信号值相同。

    Arithmetic circuit to increase the speed of a modular multiplication for a public key system for encryption
    5.
    发明授权
    Arithmetic circuit to increase the speed of a modular multiplication for a public key system for encryption 有权
    算术电路,用于增加用于加密的公钥系统的乘法运算速度

    公开(公告)号:US06772942B2

    公开(公告)日:2004-08-10

    申请号:US10023147

    申请日:2001-12-18

    IPC分类号: G06F1110

    CPC分类号: G06F9/3824 G06F7/728

    摘要: A circuit and a method for solving the Montgomery multiplier bottleneck problem encountered during a memory access using two ports or single port general-purpose memories is described. A first and a second memory are provided such that variables that are stored in one memory must be read for an operation to be recorded in the second memory. Thereafter, during a reading cycle corresponding to a pipeline process, certain of the variables are read from the first memory and are loaded in the predetermined register while the other variables are read from the second memory and are loaded in the remaining registers.

    摘要翻译: 描述了一种用于解决在使用两个端口或单端口通用存储器的存储器访问期间遇到的蒙哥马利乘数瓶颈问题的电路和方法。 提供第一和第二存储器,使得存储在一个存储器中的变量必须被读取用于要记录在第二存储器中的操作。 此后,在对应于流水线处理的读取周期期间,从第一存储器读取某些变量,并将其加载到预定寄存器中,而从第二存储器读取其他变量并将其加载到其余寄存器中。

    Radix-8 fixed-point FFT logic circuit characterized by preservation of square root-i operation
    6.
    发明授权
    Radix-8 fixed-point FFT logic circuit characterized by preservation of square root-i operation 有权
    特点是保存平方根i操作的基数为8的定点FFT逻辑电路

    公开(公告)号:US08838661B2

    公开(公告)日:2014-09-16

    申请号:US13300710

    申请日:2011-11-21

    IPC分类号: G06F17/14

    CPC分类号: G06F17/142 G06F17/141

    摘要: A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.

    摘要翻译: 一种降低快速傅里叶变换(FFT)运算误差的方法。 包含在蝴蝶操作(8p)中的复平面上的旋转因子中出现的非理性数(数平方根)的数据被有意保留,而不是在多级流水线FFT的多级的一个阶段中计算出来, 并且当在稍后阶段再次发生时,执行将两个旋转因子彼此相乘的操作。 这使得能够在基数-8的蝶形运算8p期间消除舍入误差。 其他应用也是可能的,例如通过用基数-2或基数-4的蝶形运算覆盖另外的阶段。

    Adaptation to millimeter-wave communication link using different frequency carriers
    7.
    发明授权
    Adaptation to millimeter-wave communication link using different frequency carriers 失效
    使用不同的频率载波适应毫米波通信链路

    公开(公告)号:US08755450B2

    公开(公告)日:2014-06-17

    申请号:US13479887

    申请日:2012-05-24

    IPC分类号: H04L27/00

    CPC分类号: H04L1/0025 H04L1/12

    摘要: To realize quick adaptation to a communication link between a transmitter and a receiver by using two different frequency carriers. A receiver detects a preamble from a transmission bit string. When determining that a total sum of the number of modified bits exceeds a certain threshold in a range of a payload following the preamble (when detecting that a reception state of a communication link has been degraded), the receiver issues, to a transmitter, a request for changing a transmission parameter (four parameters may be used for enhancement/lowering) for the transmission bit string by using a communication link, which is a relatively-low-frequency carrier. On the other hand, the transmitter receives the request for change, and executes the request for changing the transmission parameter for the transmission bit string while maintaining transmission of a payload in the transmission bit string.

    摘要翻译: 通过使用两个不同的频率载波来实现对发射机和接收机之间的通信链路的快速适配。 接收机从传输比特串检测前置码。 当确定在前导码之后的有效载荷的范围内(当检测到通信链路的接收状态已经劣化时)修改比特数的总和超过某个阈值时,接收机向发射机发出 通过使用作为相对低频载波的通信链路,请求改变传输比特串的传输参数(四个参数可用于增强/降低)。 另一方面,发送器接收到变更请求,并且在维持发送位串中的净荷的发送的同时执行用于变更发送位串的发送参数的请求。

    Detecting an extraordinary behavior
    8.
    发明授权
    Detecting an extraordinary behavior 有权
    检测出非凡的行为

    公开(公告)号:US08271981B2

    公开(公告)日:2012-09-18

    申请号:US11937821

    申请日:2007-11-09

    IPC分类号: G06F9/46 G06F11/00

    摘要: An apparatus detects detecting when an extraordinary behavior is performed when a monitoring task is executed on an information processing apparatus. The detecting apparatus includes: an obtaining section for obtaining a measurement data including an executing timing and an execution time for each occasion of execution when the monitoring task is executed for a number of times on the information processing apparatus; a distance calculating section for calculating a distance between a measured point corresponding to each measurement data in a multi-dimensional space on which an executing timing and an execution time are allocated to different coordinates and another measured point placed in a predetermined range; and a determining section for determining whether an extraordinary behavior is performed when the monitoring task corresponding to the measurement data is executed based on the distance obtained for the measured point corresponding to the measurement data.

    摘要翻译: 当在信息处理设备上执行监视任务时,设备检测检测何时执行异常行为。 检测装置包括:获取部,用于在信息处理装置执行监视任务多次时,获得包括执行定时和执行时间的测量数据; 距离计算部分,用于计算在执行定时和执行时间被分配给不同坐标的多维空间中对应于每个测量数据的测量点与放置在预定范围中的另一测量点之间的距离; 以及确定部,用于基于对于与测量数据相对应的测量点获得的距离来执行与测量数据相对应的监视任务时是否执行非常行为。

    METHOD AND APPARATUS FOR DETECTING PROCESSOR BEHAVIOR USING INSTRUCTION TRACE DATA
    9.
    发明申请
    METHOD AND APPARATUS FOR DETECTING PROCESSOR BEHAVIOR USING INSTRUCTION TRACE DATA 审中-公开
    使用指令跟踪数据检测处理器行为的方法和装置

    公开(公告)号:US20090222646A1

    公开(公告)日:2009-09-03

    申请号:US12039394

    申请日:2008-02-28

    IPC分类号: G06F9/40

    CPC分类号: G06F11/3636

    摘要: A method and apparatus for detecting processor behavior in real time using instruction trace data, in one aspect, identifies one or more call addresses from which a function to be observed is called and establishes one or more end addresses of the function. Said one or more call addresses and said one or more end addresses are stored, and compared with a branch address contained in the instruction trace data to detect start and end of the function dynamically in real time.

    摘要翻译: 一方面,一种用于使用指令跟踪数据实时检测处理器行为的方法和装置识别一个或多个调用地址,从该地址调用要观察的功能,并建立该功能的一个或多个结束地址。 所述一个或多个呼叫地址和所述一个或多个结束地址被存储,并且与包含在指令轨迹数据中的分支地址进行比较,以实时动态检测功能的起始和结束。

    Method, Apparatus, and Program for Detecting the Correlation Between Repeating Events
    10.
    发明申请
    Method, Apparatus, and Program for Detecting the Correlation Between Repeating Events 有权
    检测重复事件相关性的方法,装置和程序

    公开(公告)号:US20080137800A1

    公开(公告)日:2008-06-12

    申请号:US11937761

    申请日:2007-11-09

    IPC分类号: G04F13/00

    摘要: A detecting apparatus detects the degree of correlation between first events and second events repeatedly occurring in an observed apparatus includes an acquiring unit that acquires second event count values each indicating the number of second events occurring during each first period between each first event and the first event next thereto. A measuring unit measures an observed number of each second event count value derived from the number of times the second event count value is observed. A calculating unit calculates the degree of correlation between the first events and the second events based on the observed number of each second event count value.

    摘要翻译: 检测装置检测在观察装置中重复发生的第一事件与第二事件之间的相关程度包括获取单元,其获取第二事件计数值,每个第二事件计数值指示在每个第一事件和第一事件之间的每个第一周期期间发生的第二事件的数量 在其旁边。 测量单元测量从观察第二事件计数值的次数导出的每个第二事件计数值的观察次数。 计算单元基于观察到的每个第二事件计数值的数量来计算第一事件和第二事件之间的相关程度。