发明授权
- 专利标题: Semiconductor device comprising a capacitor and an electrical connection via and fabrication method
- 专利标题(中): 包括电容器和电连接通孔及其制造方法的半导体器件
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申请号: US13298735申请日: 2011-11-17
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公开(公告)号: US08841748B2公开(公告)日: 2014-09-23
- 发明人: Sylvain Joblot , Alexis Farcy , Jean-Francois Carpentier , Pierre Bar
- 申请人: Sylvain Joblot , Alexis Farcy , Jean-Francois Carpentier , Pierre Bar
- 申请人地址: FR Montrogue
- 专利权人: STMicroelectronics SA
- 当前专利权人: STMicroelectronics SA
- 当前专利权人地址: FR Montrogue
- 代理机构: Gardere Wynne Sewell LLP
- 优先权: FR1059917 20101130
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L23/58 ; H01L21/768 ; H01L23/48 ; H01L23/522
摘要:
A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.
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