Invention Grant
- Patent Title: Multi-layer interconnect structure for stacked dies
- Patent Title (中): 用于堆叠管芯的多层互连结构
-
Application No.: US13608456Application Date: 2012-09-10
-
Publication No.: US08841773B2Publication Date: 2014-09-23
- Inventor: Hung-Pin Chang , Chien-Ming Chiu , Tsang-Jiuh Wu , Shau-Lin Shue , Chen-Hua Yu
- Applicant: Hung-Pin Chang , Chien-Ming Chiu , Tsang-Jiuh Wu , Shau-Lin Shue , Chen-Hua Yu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L21/768 ; H01L21/683 ; H01L23/00 ; H01L23/525

Abstract:
A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
Public/Granted literature
- US20130001799A1 Multi-Layer Interconnect Structure for Stacked Dies Public/Granted day:2013-01-03
Information query
IPC分类: