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US08841773B2 Multi-layer interconnect structure for stacked dies 有权
用于堆叠管芯的多层互连结构

Multi-layer interconnect structure for stacked dies
Abstract:
A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
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