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    Apparatus and methods for end point determination in reactive ion etching
    2.
    发明授权
    Apparatus and methods for end point determination in reactive ion etching 有权
    用于反应离子蚀刻终点测定的装置和方法

    公开(公告)号：US08445296B2

    公开(公告)日：2013-05-21

    申请号：US13189287

    申请日：2011-07-22

    申请人： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

    发明人： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

    IPC分类号： H01L21/02

    CPC分类号： H01J37/32963

    摘要： Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

    摘要翻译： 执行终点确定的方法和装置。 一种方法包括将晶片接收到用于进行RIE蚀刻的蚀刻工具室中; 开始RIE蚀刻以在晶片中形成通孔; 接收与RIE蚀刻工艺相关的蚀刻工具室的一个或多个物理参数的原位测量; 为腔室中的RIE蚀刻提供虚拟计量模型; 将接收到的原位测量值输入到腔室中的RIE蚀刻的虚拟测量模型; 执行虚拟计量模型以通过深度估计电流; 将经过深度的估计电流与目标深度进行比较; 并且当比较指示当前经过深度在目标深度的预定阈值内时; 输出停止信号。 公开了一种用于该方法实施例的装置。

    Dual damascene process without an etch stop layer
    6.
    发明授权
    Dual damascene process without an etch stop layer 失效
    双镶嵌工艺无蚀刻停止层

    公开(公告)号：US07629690B2

    公开(公告)日：2009-12-08

    申请号：US11294140

    申请日：2005-12-05

    申请人： Tsang-Jiuh Wu ,  Syun-Ming Jang

    发明人： Tsang-Jiuh Wu ,  Syun-Ming Jang

    IPC分类号： H01L29/40 ,  H01L23/52

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductive features in the first low-k dielectric layer, a cap layer on at least a portion of the conductive features, and a dielectric capping layer overlying the first low-k dielectric layer in the second region but not in the first region. The conductive features in the second region have a substantially greater spacing than the conductive features in the first region. The dielectric capping layer preferably has an inherent compressive stress.

    摘要翻译： 提供非ESL半导体互连结构及其形成方法。 非ESL半导体互连结构包括第一低k电介质层，其包括覆盖衬底的第一区域和第二区域，第一低k电介质层中的多个导电特征，至少部分 导电特征以及覆盖第二区域中第一低k电介质层但不在第一区域中的介电覆盖层。 第二区域中的导电特征具有比第一区域中的导电特征大得多的间隔。 电介质覆盖层优选具有固有的压缩应力。

    Dual damascene process
    9.
    发明授权
    Dual damascene process 有权
    双镶嵌工艺

    公开(公告)号：US07253112B2

    公开(公告)日：2007-08-07

    申请号：US10915633

    申请日：2004-08-10

    申请人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

    发明人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76808

    摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

    摘要翻译： 使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料组成的通孔中形成插塞。 在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。 接下来，施加一层光致抗蚀剂。 然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。 使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。 蚀刻步骤被称为镶嵌蚀刻步骤。 去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

    In-situ discharge to avoid arcing during plasma etch processes
    10.
    发明授权
    In-situ discharge to avoid arcing during plasma etch processes 有权
    原位放电以避免等离子体蚀刻过程中的电弧

    公开(公告)号：US06914007B2

    公开(公告)日：2005-07-05

    申请号：US10366206

    申请日：2003-02-13

    申请人： Ching-Hui Ma ,  Chao-Cheng Chen ,  Tsang-Jiuh Wu ,  Hui-Chang Yu ,  Hun-Jan Tao

    发明人： Ching-Hui Ma ,  Chao-Cheng Chen ,  Tsang-Jiuh Wu ,  Hui-Chang Yu ,  Hun-Jan Tao

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461 ,  H01L21/462

    CPC分类号： H01J37/32009 ,  H01J2237/0206 ,  H01L21/31116 ,  H01L21/76802

    摘要： A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.

    摘要翻译： 描述了一种减少衬底上的电荷以防止在后续蚀刻工艺中的电弧入射的方法。 图案化衬底被固定到处理室中的卡盘。 执行放电处理，其包括以下三个步骤：（a）将卡盘耦合到0伏连接，（b）产生等离子体，以及（c）将卡盘耦合到高压连接。 三个步骤以任何顺序进行。 在放电顺序期间，惰性气体或惰性气体和蚀刻气体流入腔室。 或者，碳氟化合物C 1 H Z，或碳氟化合物和气体如O 2 H，H N 2，N 2，N 2 O，CO，CO 2，He或Ar流入室 在放电序列期间。 该方法与批次或单晶片工艺兼容，并且可扩展到蚀刻导热性差的低k电介质层。