发明授权
- 专利标题: Stacked wafer level package having a reduced size
- 专利标题(中): 具有减小尺寸的堆叠晶片级封装
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申请号: US13569600申请日: 2012-08-08
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公开(公告)号: US08847377B2公开(公告)日: 2014-09-30
- 发明人: Jong Hoon Kim , Min Suk Suh , Seung Taek Yang , Seung Hyun Lee , Tae Min Kang
- 申请人: Jong Hoon Kim , Min Suk Suh , Seung Taek Yang , Seung Hyun Lee , Tae Min Kang
- 申请人地址: KR Gyeonggi-do
- 专利权人: SK Hynix Inc.
- 当前专利权人: SK Hynix Inc.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: Ladas & Parry LLP
- 优先权: KR10-2008-0000317 20080102
- 主分类号: H01L23/02
- IPC分类号: H01L23/02 ; H01L21/683 ; H01L21/56 ; H01L23/538 ; H01L25/00 ; H01L25/065 ; H01L23/31 ; H01L23/00 ; H01L25/18
摘要:
A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.
公开/授权文献
- US20120299169A1 STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE 公开/授权日:2012-11-29
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