公开(公告)号：US08847377B2

公开(公告)日：2014-09-30

申请号：US13569600

申请日：2012-08-08

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Tae Min Kang

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Tae Min Kang

IPC分类号： H01L23/02 ,  H01L21/683 ,  H01L21/56 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2224/19 ,  H01L2924/00

摘要： A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

摘要翻译： 堆叠的晶片级封装包括具有第一焊盘的第一半导体芯片和具有第二焊盘的第二半导体芯片。 半导体芯片的两个接合焊盘面向相同的方向。 第二半导体芯片与第一半导体芯片平行设置。 第三半导体芯片设置在用作支撑衬底的第一和第二半导体芯片上。 第三半导体芯片具有在附接时在第一和第二半导体芯片之间露出的第三焊盘。 最后，再分布结构电连接到第一，第二和第三键合焊盘。

公开(公告)号：US08395245B2

公开(公告)日：2013-03-12

申请号：US11953967

申请日：2007-12-11

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

IPC分类号： H01L23/495

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

摘要翻译： 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US08361838B2

公开(公告)日：2013-01-29

申请号：US13241812

申请日：2011-09-23

申请人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

摘要： A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

摘要翻译： 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

公开(公告)号：US08018043B2

公开(公告)日：2011-09-13

申请号：US12261112

申请日：2008-10-30

申请人： Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/4334 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311

摘要： A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

摘要翻译： 半导体封装包括具有上表面的半导体芯片，与上表面连接的侧表面，以及形成在上表面上的焊盘。 形成第一绝缘层图案以覆盖半导体芯片的上表面和侧表面并且暴露接合焊盘。 再分配线路放置在第一绝缘层图案上，并且包括第一再分配线部分和第二再分配线部分。 第一再分配线部分具有与接合焊盘连接的端部并且对应于半导体芯片的上表面，并且第二再分配线部分从第一再分配线部分延伸超过半导体芯片的侧表面 。 在半导体芯片上形成第二绝缘层图案，并且暴露出第一再分配线部分和第二再分配线部分的部分。

公开(公告)号：US08049341B2

公开(公告)日：2011-11-01

申请号：US12244322

申请日：2008-10-02

申请人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L23/52

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

摘要： A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

摘要翻译： 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

公开(公告)号：US07795139B2

公开(公告)日：2010-09-14

申请号：US11777388

申请日：2007-07-13

申请人： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

发明人： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

摘要翻译： 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US07859115B2

公开(公告)日：2010-12-28

申请号：US12346963

申请日：2008-12-31

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seung Taek Yang

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seung Taek Yang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants.

摘要翻译： 半导体封装包括具有第一区域和第二区域的半导体芯片。 形成接合焊盘并且在第一和第二区域中限定通孔。 绝缘层形成在通孔的侧壁上，通孔形成在通孔中并与相应的接合焊盘连接。 形成在第一和第二区域中的绝缘层具有不同的厚度或介电常数。

公开(公告)号：US07446405B2

公开(公告)日：2008-11-04

申请号：US11648281

申请日：2006-12-29

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05099

摘要： A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.

摘要翻译： 晶片级芯片级封装包括具有多个焊盘的半导体芯片; 在半导体芯片上形成的具有1〜5GPa的高杨氏模量的下部绝缘层，以露出多个焊盘; 多个金属图案形成在下绝缘层上以连接到相应的焊盘; 形成在下绝缘层上的具有1〜5GPa的高杨氏模量的上绝缘层和金属图案以部分地暴露金属图案; 以及形成在金属图案的暴露部分上的多个焊球。

公开(公告)号：US20070182022A1

公开(公告)日：2007-08-09

申请号：US11648281

申请日：2006-12-29

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05099

摘要： A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.

摘要翻译： 晶片级芯片级封装包括具有多个焊盘的半导体芯片; 在半导体芯片上形成的具有1〜5GPa的高杨氏模量的下部绝缘层，以露出多个焊盘; 多个金属图案形成在下绝缘层上以连接到相应的焊盘; 形成在下绝缘层上的具有1〜5GPa的高杨氏模量的上绝缘层和金属图案以部分地暴露金属图案; 以及形成在金属图案的暴露部分上的多个焊球。

公开(公告)号：US08299592B2

公开(公告)日：2012-10-30

申请号：US12489626

申请日：2009-06-23

申请人： Min Suk Suh ,  Seung Hyun Lee

发明人： Min Suk Suh ,  Seung Hyun Lee

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L29/40

CPC分类号： H01L23/481 ,  H01L24/17 ,  H01L24/24 ,  H01L24/29 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16146 ,  H01L2224/24145 ,  H01L2224/29101 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00

摘要： A cube semiconductor package includes one or more stacked together and interconnected semiconductor chip modules. The cube semiconductor package includes a semiconductor chip module and connection members. The semiconductor chip module includes a semiconductor chip which has a first and second surface, side surfaces, bonding pads, through-electrodes and redistribution lines. The second surface faces away from the first surface. The side surfaces connect to the first and second surfaces. The bonding pads are placed on the first surface. The through-electrodes pass through the first and second surfaces. The redistribution lines are placed at least on one of the first and second surfaces and are electrically connected to the through-electrodes and the bonding pads, and have ends flush with the side surfaces. The connection members are placed on the side surfaces and electrically connected with the ends of the redistribution lines.

摘要翻译： 立方体半导体封装包括一个或多个堆叠在一起并且互连的半导体芯片模块。 立方体半导体封装包括半导体芯片模块和连接构件。 半导体芯片模块包括具有第一和第二表面，侧表面，接合焊盘，通孔和再分配线的半导体芯片。 第二表面背离第一表面。 侧表面连接到第一和第二表面。 接合垫被放置在第一表面上。 贯通电极通过第一和第二表面。 再分配线至少放置在第一表面和第二表面中的一个上，并且电连接到通孔和接合焊盘，并且具有与侧表面齐平的端部。 连接构件放置在侧面上并与再分配线的端部电连接。