Invention Grant
- Patent Title: Method of manufacturing semiconductor circuit structure
- Patent Title (中): 制造半导体电路结构的方法
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Application No.: US14094806Application Date: 2013-12-03
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Publication No.: US08850370B2Publication Date: 2014-09-30
- Inventor: Chia-Chen Sun , Shih-Chieh Hsu , Yi-Chung Sheng , Sheng-Yuan Hsueh , Yao-Chang Wang
- Applicant: United Microelectronics Corporation
- Applicant Address: TW Hsinchu
- Assignee: United Microelectronics Corporation
- Current Assignee: United Microelectronics Corporation
- Current Assignee Address: TW Hsinchu
- Agent Ding Yu Tan
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/528

Abstract:
A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.
Public/Granted literature
- US20140089869A1 LAYOUT METHOD OF SEMICONDUCTOR CIRCUIT STRUCTURE Public/Granted day:2014-03-27
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