公开(公告)号：US08850370B2

公开(公告)日：2014-09-30

申请号：US14094806

申请日：2013-12-03

Applicant: United Microelectronics Corporation

Inventor： Chia-Chen Sun ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

IPC: G06F17/50 ,  H01L23/528

CPC classification number: G06F17/5081 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract translation: 提供了半导体电路的布局方法。 布局方法是首先在基板上放置多个电路图案，其中第一距离是任何一个电路图案与与其相邻的其它电路图案之一之间的最大距离。 布局方法然后确定第一距离是否大于第一临界值。 之后，当第一距离大于第一临界值时，至少一个闭环虚拟图形被放置在对应于该对电路图形之间的第一距离的一个区域中。 闭环虚拟图案被放置在与电路图案相同的层中，围绕在一对电路图案之间并与电路图案绝缘。

公开(公告)号：US20140089869A1

公开(公告)日：2014-03-27

申请号：US14094806

申请日：2013-12-03

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Chen SUN ,  Shih Chieh Hsu ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Yao-Chang Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract translation: 提供了半导体电路的布局方法。 布局方法是首先在基板上放置多个电路图案，其中第一距离是任何一个电路图案与与其相邻的其它电路图案之一之间的最大距离。 布局方法然后确定第一距离是否大于第一临界值。 之后，当第一距离大于第一临界值时，至少一个闭环虚拟图形被放置在对应于该对电路图形之间的第一距离的一个区域中。 闭环虚拟图案被放置在与电路图案相同的层中，围绕在一对电路图案之间并与电路图案绝缘。