Invention Grant
US08853752B2 Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
有权
通过提供相对于衬底表面具有适当角度的分级嵌入式应变诱导半导体区域来提高晶体管的性能
- Patent Title: Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
- Patent Title (中): 通过提供相对于衬底表面具有适当角度的分级嵌入式应变诱导半导体区域来提高晶体管的性能
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Application No.: US13661188Application Date: 2012-10-26
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Publication No.: US08853752B2Publication Date: 2014-10-07
- Inventor: El Mehdi Bazizi , Alban Zaka , Gabriela Dilliway , Bo Bai
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.
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