发明授权
US08856546B2 Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures 有权
使用单指令多数据(SIMD)架构加快安全散列算法(SHA)

Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures
摘要:
A processing apparatus may comprise logic to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks, logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks, and logic to generate a message digest conforming to the selected SHA algorithm.
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