发明授权
- 专利标题： Vertical channel transistor with self-aligned gate electrode and method for fabricating the same
- 专利标题（中）： 具有自对准栅电极的垂直沟道晶体管及其制造方法
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申请号： US13605550申请日： 2012-09-06
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公开(公告)号： US08860127B2公开(公告)日： 2014-10-14
- 发明人: Heung-Jae Cho , Eui-Seong Hwang , Eun-Shil Park
- 申请人： Heung-Jae Cho , Eui-Seong Hwang , Eun-Shil Park
- 申请人地址： KR Gyeonggi-do
- 专利权人： SK Hynix Inc.
- 当前专利权人： SK Hynix Inc.
- 当前专利权人地址： KR Gyeonggi-do
- 代理机构： IP & T Group LLP
- 优先权： KR10-2012-0058607 20120531
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L29/78
摘要：
A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
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