Invention Grant
US08860598B2 Bit error rate timer for a dynamic latch 有权
动态锁存器的位错误率定时器

Bit error rate timer for a dynamic latch
Abstract:
A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.
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