Invention Grant
- Patent Title: Bit error rate timer for a dynamic latch
- Patent Title (中): 动态锁存器的位错误率定时器
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Application No.: US13839972Application Date: 2013-03-15
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Publication No.: US08860598B2Publication Date: 2014-10-14
- Inventor: Frederick Carnegie Thompson , John Cullinane
- Applicant: Analog Devices Technology
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Technology
- Current Assignee: Analog Devices Technology
- Current Assignee Address: BM Hamilton
- Agency: Kenyon & Kenyon, LLP
- Main IPC: H03M1/60
- IPC: H03M1/60 ; H03M1/14

Abstract:
A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.
Public/Granted literature
- US20140266842A1 BIT ERROR RATE TIMER FOR A DYNAMIC LATCH Public/Granted day:2014-09-18
Information query
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