Invention Grant
- Patent Title: Test circuit and method of semiconductor memory apparatus
- Patent Title (中): 半导体存储器件的测试电路和方法
-
Application No.: US13586047Application Date: 2012-08-15
-
Publication No.: US08867287B2Publication Date: 2014-10-21
- Inventor: Jin Youp Cha , Jae Il Kim
- Applicant: Jin Youp Cha , Jae Il Kim
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2012-0056009 20120525
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/44 ; G11C29/40 ; G11C29/12 ; G11C29/14

Abstract:
A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
Public/Granted literature
- US20130315007A1 TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS Public/Granted day:2013-11-28
Information query