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    Semiconductor memory device and operating method thereof
    1.
    发明授权
    Semiconductor memory device and operating method thereof 有权

    公开(公告)号：US11640843B2

    公开(公告)日：2023-05-02

    申请号：US17220284

    申请日：2021-04-01

    申请人： SK hynix Inc.

    发明人： Noh Hyup Kwak

    IPC分类号： G11C29/38 ,  G11C7/10 ,  G11C29/14 ,  G11C29/44 ,  H03K3/038 ,  G01R31/3185

    摘要： According to an embodiment of the present disclosure, a semiconductor memory device includes a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes; and a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes, wherein each of the write mode register sets includes: a storing circuit suitable for storing an operational code according to a mode register write command; and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal.

    SEMICONDUCTOR MEMORY DEVICE DETECTING DEFECT, AND OPERATING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE DETECTING DEFECT, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230121078A1

    公开(公告)日：2023-04-20

    申请号：US17954663

    申请日：2022-09-28

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Bongkil JUNG ,  Sangwan NAM ,  Keeho JUNG

    IPC分类号： G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/20

    摘要： Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.

    SYSTEM FOR OUTPUTTING TEST DATA FROM MULTIPLE CORES AND METHOD THEREOF
    4.
    发明申请
    SYSTEM FOR OUTPUTTING TEST DATA FROM MULTIPLE CORES AND METHOD THEREOF 有权

    公开(公告)号：US20230092302A1

    公开(公告)日：2023-03-23

    申请号：US17482151

    申请日：2021-09-22

    申请人： SK hynix Inc.

    发明人： Siarhei Rusakovich

    IPC分类号： G11C29/36 ,  G11C29/44 ,  G11C29/10 ,  G11C29/14 ,  G11C7/10

    摘要： A system for outputting test data from cores to one communication interface. The system includes shared memories corresponding to the cores. Each shared memory includes a ring buffer and an array of slots. Each core generates a diagnostic message, and stores the generated diagnostic message in a select memory region of the ring buffer corresponding to a first empty slot of the array of slots. A selected core finds a first diagnostic message among diagnostic messages stored in the shared memories, and outputs the first diagnostic message to a personal computer through the communication interface.

    Direct testing of in-package memory
    5.
    发明授权
    Direct testing of in-package memory 有权

    公开(公告)号：US11587633B2

    公开(公告)日：2023-02-21

    申请号：US17349612

    申请日：2021-06-16

    申请人： Micron Technology, Inc.

    发明人： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

    IPC分类号： G11C29/10 ,  G11C29/36 ,  G11C29/14 ,  G11C29/18 ,  G11C29/12

    摘要： Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

    Electrical testing apparatus for spintronics devices
    6.
    发明授权
    Electrical testing apparatus for spintronics devices 有权

    公开(公告)号：US11573270B2

    公开(公告)日：2023-02-07

    申请号：US17365822

    申请日：2021-07-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Guenole Jan ,  Huanlong Liu ,  Jian Zhu ,  Yuan-Jen Lee ,  Po-Kang Wang

    IPC分类号： G01R31/319 ,  G11C29/14 ,  G11C29/38 ,  G11C29/12 ,  G01R31/3167 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/263 ,  G11C11/16 ,  H03M1/12

    摘要： A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

    SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED METHODS AND SYSTEMS
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20230014661A1

    公开(公告)日：2023-01-19

    申请号：US17935057

    申请日：2022-09-23

    申请人： Micron Technology, Inc.

    发明人： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

    IPC分类号： G11C29/12 ,  G11C29/44 ,  G11C11/406 ,  G11C7/10 ,  G11C29/14

    摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.