发明授权
- 专利标题： Test circuit and method of semiconductor memory apparatus
- 专利标题（中）： 半导体存储器件的测试电路和方法
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申请号： US13586047申请日： 2012-08-15
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公开(公告)号： US08867287B2公开(公告)日： 2014-10-21
- 发明人: Jin Youp Cha , Jae Il Kim
- 申请人： Jin Youp Cha , Jae Il Kim
- 申请人地址： KR Gyeonggi-do
- 专利权人： SK Hynix Inc.
- 当前专利权人： SK Hynix Inc.
- 当前专利权人地址： KR Gyeonggi-do
- 代理机构： William Park & Associates Patent Ltd.
- 优先权： KR10-2012-0056009 20120525
- 主分类号： G11C29/00
- IPC分类号： G11C29/00 ; G11C29/44 ; G11C29/40 ; G11C29/12 ; G11C29/14
摘要：
A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
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