发明授权
US08877628B2 Methods of forming nano-scale pores, nano-scale electrical contacts, and memory devices including nano-scale electrical contacts, and related structures and devices
有权
形成纳米尺度孔隙,纳米尺度电接点以及包括纳米尺度电接点的存储器件以及相关结构和器件的方法
- 专利标题: Methods of forming nano-scale pores, nano-scale electrical contacts, and memory devices including nano-scale electrical contacts, and related structures and devices
- 专利标题(中): 形成纳米尺度孔隙,纳米尺度电接点以及包括纳米尺度电接点的存储器件以及相关结构和器件的方法
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申请号: US13547228申请日: 2012-07-12
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公开(公告)号: US08877628B2公开(公告)日: 2014-11-04
- 发明人: Jun Liu , Kunal R. Parekh
- 申请人: Jun Liu , Kunal R. Parekh
- 申请人地址: US ID Boise
- 专利权人: Micron Technologies, Inc.
- 当前专利权人: Micron Technologies, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: TraskBritt
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
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