发明授权
- 专利标题： Reducing variation in multi-die integrated circuits
- 专利标题（中）： 减少多芯片集成电路的变化
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申请号： US12835184申请日： 2010-07-13
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公开(公告)号： US08886481B1公开(公告)日： 2014-11-11
- 发明人: Arifur Rahman , Michael J. Hart , Venkatesan Murali
- 申请人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 Kevin T. Cuenot; Lois D. Cartier
- 主分类号： G06F19/00
- IPC分类号： G06F19/00
摘要：
A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.
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